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(Som) Fix bug in UttVP+RelVP
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@@ -164,6 +164,14 @@ oper
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_ => P3_Prep
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} ;
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pagr2agr : PrepAgr -> Agreement = \a -> case a of {
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Sg1_Prep => Sg1 ;
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Sg2_Prep => Sg2 ;
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Pl1_Prep i => Pl1 i ;
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Pl2_Prep => Pl2 ;
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_ => Pl3
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} ;
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isP3 = overload {
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isP3 : Agreement -> Bool = \agr ->
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case agr of {Sg3 _ | Pl3 => True ; _ => False} ;
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